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3 Volt Advanced+ Stacked Chip Scale Package Memory
28F1602C3, 28F1604C3, 28F3204C3
Preliminary Datasheet
Product Features
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Flash Memory Plus SRAM -- Reduces Memory Board Space Required, Simplifying PCB Design Complexity Stacked Chip Scale Package Technology -- Smallest Memory Subsystem Footprint -- 16-Mbit Flash + 2-Mbit SRAM: Area: 8 mm by 10 mm, Height: 1.4 mm -- 32-Mbit Flash + 4-Mbit SRAM, 16-Mbit Flash + 4-Mbit SRAM: Area: 8 mm by 12 mm, Height: 1.4 mm Advanced SRAM Technology -- 70 ns Access Time -- Low Power Operation -- Low Voltage Data Retention Mode Flash Data Integrator (FDI) Software -- Real-Time Data Storage and Code Execution in the Same Memory Device -- Full Flash File Manager Capability
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Advanced+ Boot Block Flash Memory -- 90 ns 16-Mb Access Time at 2.7 V -- 100 ns 32-Mb Access Time at 2.7 V -- Instant, Individual Block Locking -- 128-bit Protection Register -- 12 V Production Programming -- Ultra Fast Program and Erase Suspend -- Extended Temperature -40 C to +85 C Blocking Architecture -- Block Sizes for Code + Data Storage -- 4-Kword Parameter Blocks (for data) -- 64-Kbyte Main Blocks (for code) -- 1,000,000 Erase Cycles per Block Low Power Operation -- Async Read Current: 9 mA -- Standby Current: 10 A -- Automatic Power Saving Mode 0.25 m ETOXTM VI Flash Technology Industry Compatibility -- Sourcing Flexibility and Stability
The 3 Volt Advanced+ Stacked Chip Scale Package (Stacked-CSP) memory delivers a featurerich solution for low-power applications. Stacked-CSP memory devices incorporate flash memory and static RAM in one package with low voltage capability to achieve the smallest system memory solution form-factor together with high-speed, low-power operations. The flash memory offers a protection register and flexible block locking to enable next generation security capability. Combined with the Intel-developed Flash Data Integrator (FDI) software, the Stacked-CSP memory provides you with a cost-effective, flexible, code plus data storage solution.
Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 290666-005 February, 2000
Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 28F1602C3, 28F1604C3, 28F3204C3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation 1999-2000 *Other brands and names are the property of their respective owners.
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Contents
1.0 Introduction .................................................................................................................. 1
1.1 1.2 1.3 1.4 Document Conventions ......................................................................................... 1 Product Overview .................................................................................................. 1 Package Ballout .................................................................................................... 2 Signal Definitions................................................................................................... 3 Bus Operation ....................................................................................................... 5 2.1.1 Read......................................................................................................... 5 2.1.2 Output Disable.......................................................................................... 6 2.1.3 Standby .................................................................................................... 6 2.1.4 Flash Reset .............................................................................................. 7 2.1.5 Write ......................................................................................................... 7 Read Array (FFH).................................................................................................. 7 Read Identifier (90H) ............................................................................................. 7 Read Status Register (70H) .................................................................................. 8 3.3.1 Clear Status Register (50H) ..................................................................... 8 Read Query (98H) .................................................................................................9 Word Program (40H/10H) ..................................................................................... 9 3.5.1 Suspending and Resuming Program (B0H/D0H) ..................................... 9 Block Erase (20H) ...............................................................................................10 3.6.1 Suspending and Resuming Erase (B0H/D0H) .......................................10 Instant, Individual Block Locking .........................................................................12 3.7.1 Block Locking Operation Summary ........................................................13 3.7.2 Locked State ..........................................................................................13 3.7.3 Unlocked State .......................................................................................13 3.7.4 Lock-Down State ....................................................................................13 3.7.5 Reading a Block's Lock Status ...............................................................14 3.7.6 Locking Operation during Erase Suspend..............................................14 3.7.7 Status Register Error Checking..............................................................14 128-Bit Protection Register .................................................................................15 3.8.1 Reading the Protection Register ............................................................15 3.8.2 Programming the Protection Register (C0H)..........................................15 3.8.3 Locking the Protection Register .............................................................16 Additional Flash Features....................................................................................16 3.9.1 Improved 12 Volt Production Programming ...........................................16 3.9.2 F-VPP VPPLK for Complete Protection .................................................17 Absolute Maximum Ratings.................................................................................17 Operating Conditions...........................................................................................18 Capacitance ........................................................................................................18 DC Characteristics ..............................................................................................19 Flash AC Characteristics--Read Operations ......................................................23 Flash AC Characteristics--Write Operations ......................................................24
2.0
Principles of Operation............................................................................................5
2.1
3.0
Flash Memory Modes of Operation.....................................................................7
3.1 3.2 3.3 3.4 3.5 3.6 3.7
3.8
3.9
4.0
Electrical Specifications........................................................................................17
4.1 4.2 4.3 4.4 4.5 4.6
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4.7 4.8 4.9 4.10 4.11
Flash Erase and Program Timings...................................................................... 25 Flash Reset Operations ...................................................................................... 27 SRAM AC Characteristics--Read Operations .................................................... 28 SRAM AC Characteristics--Write Operations .................................................... 30 SRAM Data Retention Characteristics--Extended Temperature........................ 31
5.0 6.0
Migration Guide Information ............................................................................... 32 System Design Considerations.......................................................................... 33
6.1 Background ......................................................................................................... 33 6.1.1 Flash + SRAM Footprint Integration....................................................... 33 6.1.2 Advanced+ Boot Block Flash Memory Features .................................... 33 Flash Control Considerations.............................................................................. 33 6.2.1 F-RP# Connected to System Reset ....................................................... 34 6.2.2 F-VCC, F-VPP and F-RP# Transition....................................................... 34 Noise Reduction.................................................................................................. 35 Simultaneous Operation...................................................................................... 36 6.4.1 SRAM Operation during Flash "Busy" .................................................... 36 6.4.2 Simultaneous Bus Operations................................................................ 37 Printed Circuit Board Notes................................................................................. 37 System Design Notes Summary ......................................................................... 37
6.2
6.3 6.4
6.5 6.6
7.0 8.0
Ordering Information.............................................................................................. 38 Additional Information ........................................................................................... 38 Program/Erase Flowcharts ............................................................................. 39 CFI Query Structure........................................................................................... 45 Word-Wide Memory Map Diagrams............................................................. 52 Device ID Table.................................................................................................... 54 Protection Register Addressing................................................................... 55 Mechanical and Shipping Media Details ................................................... 56
Appendix A Appendix B Appendix C Appendix D Appendix E Appendix F
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Revision History
Date of Revision 03/30/99 04/26/99 Version -001 -002 Original version Corrected title headings in Appendix B Removed reference to 8-Mbit devices, Appendix B, Table B7, Device Geometry Definition Corrected 4-Mb SRAM ICC2 specification Removed extra SRAM standby mode Clarified Locking Operations Flowchart (Appendix A) Added 16Mbit Flash + 4Mbit SRAM product references Clarified Operating Mode Table (Section 4.1.2) Clarified "Unlock" in Command Bus Definitions Table (Section 5.0) Updated DC characteristics VIL ,VIH ,and ICCD (Section 9.4) Updated AC characteristics tEHQZ (Section 9.5) Updated AC characteristics tLZ (Section 9.9) Removed 3.0-3.3V specifications (Section 9.5 and Section 9.6) Increased Erase Cycles per Block to 1,000,000 Pinout Update (Figure 1) Operating Modes clarifications (Table 3) Clarified product proliferations Structure/Text of document simplified for readability Datasheet changed to "Preliminary" status Description
06/15/99 08/11/99
-003 -004
01/20/00
-005
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1.0
Introduction
This document contains the specifications for the 3 Volt Advanced+ Stacked Chip Scale Package (Intel(R) Stacked-CSP) memory. These stacked memory solutions are offered in the following combinations: 32-Mbit flash + 4-Mbit SRAM, 16-Mbit flash + 4-Mbit SRAM, or 16-Mbit flash memory + 2-Mbit SRAM.
1.1
Document Conventions
Throughout this document, the following conventions have been adopted.
* Voltages: "2.7 V" refers to the full voltage range, 2.7 V-3.3V; 12 V refers to 11.4 V to 12.6 V * Main block(s): 32-Kword block * Parameter block(s): 4-Kword block
1.2
Product Overview
The 3 Volt Advanced+ Stacked-CSP combines flash and SRAM into a single package. The Intel Stacked-CSP memory provides secure low-voltage memory solutions for portable applications. This memory family combines two memory technologies, flash memory and SRAM, in one package. The flash memory delivers enhanced security features, a block locking capability that allows instant locking/unlocking of any flash block with zero-latency, and a 128-bit protection register that enable unique device identification, to meet the needs of next generation portable applications. Improved 12 V production programming can be used to improve factory throughput.
Table 1.
Block Organization (x16)(1)
Memory Device 32-Mbit Flash 16-Mbit Flash 2-Mbit SRAM 4-Mbit SRAM NOTE: 1. All words are 16 bits each. Kwords 2048 1024 128 256
The flash device is asymmetrically-blocked to enable system integration of code and data storage in a single device. Each flash block can be erased independently of the others up to 1,000,000 times. The flash has eight 8-KB parameter blocks located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The remaining flash memory is grouped into 32-Kword main blocks. Any individual flash block can be locked or unlocked instantly to provide complete protection for code or data (see Section 4.7, "Flash Erase and Program Timings(1)" on page 25 for details). The flash contains both a Command User interface (CUI) and a Write State Machine (WSM). The CUI serves as the interface between the microcontroller and the internal operation of the flash memory. The internal WSM automatically executes the algorithms and timings necessary for
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program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The flash's status register indicates the status of the WSM by signifying block erase or word program completion and status. Flash program and erase automation allows program and erase operations to be executed using an industry-standard two-write command sequence to the CUI. Program operations are performed in word increments. Erase operations erase all locations within a block simultaneously. Both program and erase operations can be suspended by the system software in order to read from any other flash block. In addition, data can be programmed to another flash block during an erase suspend. 3 Volt Advanced+ Stacked-CSP memories offer two low-power savings features: Automatic Power Savings (APS) for flash memory and standby mode for flash and SRAM. The device automatically enters APS mode following the completion of a read cycle from the flash memory. Standby mode is initiated when the system deselects the device by driving F-CE# and S-CS1# or S-CS2 inactive. Power savings features significantly reduce power consumption. The flash memory can be reset by lowering F-RP# to GND. This provides CPU-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/-down sequences.
1.3
72-
Package Ballout
Figure 1. 72-Ball Stacked Chip Scale Package
1 A NC B
2
3 A20 A16
4 A11 A8
5 A15 A10 A21
6 A14 A9
7 A13
8
9
10
11
12 NC
A12 F-V SS F-VCCQ
DQ15 S-WE# DQ 14 DQ7 DQ13 DQ 6 DQ4 DQ5
C F-WE# NC D S-V SS F-RP# A22 E F-WP# VPP F S-LB# S-UB# S-OE# G A18 H NC NC A5 A4 A0 F-CE# F-V SS F-OE# NC NC A17 A7 A6 A3 A2 A1 S-CS 1# DQ 9 DQ 8 DQ0 DQ1 A19 DQ11 DQ 10 DQ2 DQ3 DQ12 S-CS 2 S-V CC F-V CC
Top View, Balls Down
NOTE: Flash upgrade address lines are shown for A21 (64-Mbit flash) and A22 (128-Mbit flash). In all flash and SRAM combinations, 66 balls are populated (A21 and A22 are not populated). Location A10 is "NC" on 16/2 devices only.
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1.4
Signal Definitions
Table 2. defines the signal definitions shown in the previous ballout.
Table 2.
Symbol
3 Volt Advanced+ Stacked-CSP Ball Descriptions
Type Name and Function ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle.
A0-A20
INPUT
Flash: 16-Mbit x 16, A[0-19]; 32-Mbit x 16, A[0-20] SRAM: 2-Mbit x 16, A[0-16]; 4-Mbit x 16, A[0-17] DATA INPUTS/OUTPUTS: Inputs array data for SRAM write operations and on the second F-CE# and F-WE# cycle during a flash Program command. Inputs commands to the flash's Command User Interface when F-CE# and F-WE# are active. Data is internally latched. Outputs array, configuration and status register data. The data balls float to tri-state when the chip is de-selected or the outputs are disabled. FLASH CHIP ENABLE: Activates the flash internal control logic, input buffers, decoders and sense amplifiers. F-CE# is active low. F-CE# high de-selects the flash memory device and reduces power consumption to standby levels. SRAM CHIP SELECT1: Activates the SRAM internal control logic, input buffers, decoders and sense amplifiers. S-CS1# is active low. S-CS1# high de-selects the SRAM memory device and reduces power consumption to standby levels. SRAM CHIP SELECT2: Activates the SRAM internal control logic, input buffers, decoders and sense amplifiers. S-CS2 is active high. S-CS2 low de-selects the SRAM memory device and reduces power consumption to standby levels. FLASH OUTPUT ENABLE: Enables flash's outputs through the data buffers during a read operation. F-OE# is active low. SRAM OUTPUT ENABLE: Enables SRAM's outputs through the data buffers during a read operation. S-OE# is active low. FLASH WRITE ENABLE: Controls writes to flash's command register and memory array. F-WE# is active low. Addresses and data are latched on the rising edge of the second F-WE# pulse. SRAM WRITE ENABLE: Controls writes to the SRAM memory array. S-WE# is active low. SRAM UPPER BYTE ENABLE: Enables the upper bytes for SRAM (DQ8-DQ15). S-UB# is active low. SRAM LOWER BYTE ENABLE: Enables the lower bytes for SRAM (DQ0-DQ7). S-LB# is active low. FLASH RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-down mode.
DQ0- DQ15
INPUT / OUTPUT
F-CE#
INPUT
S-CS1#
INPUT
S-CS2 F-OE# S-OE# F-WE# S-WE# S-UB# S-LB#
INPUT
INPUT INPUT INPUT INPUT INPUT INPUT
F-RP#
INPUT
When F-RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). When F-RP# is at logic high, the device is in standard operation. When F-RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. FLASH WRITE PROTECT: Controls the lock-down function of the flexible Locking feature. When F-WP# is a logic low, the lock-down mechanism is enabled and blocks marked lockdown cannot be unlocked through software.
F-WP#
INPUT
When F-WP# is logic high, the lock-down mechanism is disabled and blocks previously locked-down are now locked and can be unlocked and locked through software. After F-WP# goes low, any blocks previously marked lock-down revert to that state. See Section 6.0 for details on block locking. FLASH POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device core operations. FLASH I/O POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device I/O operations.
F-VCC F-VCCQ
SUPPLY SUPPLY
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Table 2.
Symbol S-VCC
3 Volt Advanced+ Stacked-CSP Ball Descriptions
Type SUPPLY Name and Function SRAM POWER SUPPLY: [2.7 V-3.3 V] Supplies power for device operations. See Section 6.2.2 for details of power connections. FLASH PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.3 V or 11.4 V-12.6 V] Operates as an input at logic levels to control complete flash protection. Supplies power for accelerated flash program and erase operations in 12 V 5% range. This ball cannot be left floating. Lower F-VPP VPPLK, to protect all contents against Program and Erase commands. INPUT / SUPPLY Set F-VPP = F-VCC for in-system read, program and erase operations. In this configuration, F-VPP can drop as low as 1.65 V to allow for resistor or diode drop from the system supply. Note that if F-VPP is driven by a logic signal, VIH = 1.65 V. That is, F-VPP must remain above 1.65 V to perform in-system flash modifications. Raise F-VPP to 12 V 5% for faster program and erase in a production environment. Applying 12 V 5% to F-VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum.
F-VPP
F-GND S-GND NC
SUPPLY SUPPLY
FLASH GROUND: For all internal circuitry. All ground inputs must be connected. SRAM GROUND: For all internal circuitry. All ground inputs must be connected. NOT CONNECTED: Internally disconnected within the device.
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2.0
Principles of Operation
The flash memory utilizes a CUI and automated algorithms to simplify program and erase operations. The WSM automates program and erase operations by handling data and address latches, WE#, and system status requests.
Figure 2. 3 Volt Advanced+ Stacked Chip Scale Package Block Diagram
F-VCC F-VPP F-GND
F-CE# F-OE# F-WE# F-RP# F-WP# A17-19/A18-20 A0-16/A0-17 S-CS1# S-CS2 S-OE# S-WE# S-UB# S-LB#
1,048,576 x16 bit (16 Mbit) 2,097,152 x16 bit (32 Mbit) 3 Volt Advanced+ Boot Block Flash Memory
DQ0-15
131,072 x16 bit (2 Mbit) 262,144 x16 bit (4 Mbit) SRAM
S-VCC
.
S-GND
2.1
Bus Operation
All bus cycles to or from the Stacked-CSP conform to standard microcontroller bus cycles. Four control signals dictate the data flow in and out of the flash component: F-CE#, F-OE#, F-WE# and F-RP#. Four separate control signals handle the data flow in and out of the SRAM component: S-CS1#, S-CS2, S-OE#, and S-WE#. These bus operations are summarized in Table 2 and Table 3.
2.1.1
Read
The flash memory has four read modes: read array, read identifier, read status and read query. These flash memory read modes are not dependent on the F-VPP voltage. Upon initial device power-up or after exit from reset, the flash device automatically defaults to read array mode. FCE# and F-OE# must be driven active to obtain data from the flash component. The SRAM has one read mode available. S-CS1#, S-CS2, and S-OE# must be driven active to obtain data from the SRAM device. See Table 3, "Recommended Memory System Operating Mode Summary" on page 6 for a summary of operations.
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Table 3.
Recommended Memory System Operating Mode Summary
Flash Signals SRAM Signals Memory Output Memory Bus Control
S-WE#
F-WE#
S-OE#
F-OE#
F-RP#
F-CE#
S-CS2
Modes
S-CS1#
D0 - D15
Notes
Read FLASH Write Standby Output Disable Reset Read Write SRAM Standby
H H H H L
L L H L X
L H X H X
H SRAM must be in High Z L X H X L L H X H H X L H L H X X H H L X Any SRAM mode is allowable
Flash Flash Other Other Other SRAM SRAM Other X X Other Other
DOUT DIN High Z High Z High Z DOUT DIN High Z High Z High Z
1,2,6 1,6 3,4 3,4 3,4 1,6 1,6 3,4,6 3,4,6 3,5,6
FLASH must be in High Z
Any FLASH mode is allowable Output Disable Data Retention L
same as a standby
NOTES: 1. Two devices may not drive the memory bus at the same time. 2. Allowable flash read modes include read array, read query, read configuration, and read status. 3. Outputs are dependent on a separate device controlling bus outputs. 4. Modes of the flash and SRAM can be interleaved so that while one is disabled, the other controls outputs. 5. The SRAM may be placed into data retention mode by lowering the S-VCC to the VDR range, as specified. 6. SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2 7. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to control the bus outputs at a time.
2.1.2
Output Disable
With F-OE# and S-OE# inactive, the Stacked-CSP outputs are disabled output balls are placed in a high-impedance state.
2.1.3
Standby
With F-CE# and S-CS1# or S-CS2 inactive, the Stacked-CSP enters a standby mode, which substantially reduces device power consumption. In standby, outputs are placed in a highimpedance state independent of F-OE# and S-OE#. If the flash is deselected during a program or erase operation, the flash continues to consume active power until the program or erase operation is complete.
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2.1.4
Flash Reset
The device enters a reset mode when RP# is driven low. In reset mode, internal circuitry is turned off and outputs are placed in a high-impedance state. After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The device defaults to read array mode, the status register is set to 80H, and the read configuration register defaults to asynchronous reads. If RP# is taken low during a block erase or program operation, the operation will be aborted and the memory contents at the aborted location are no longer valid.
2.1.5
Write
Writes to flash take place when both F-CE# and F-WE# are low and F-OE# is high. Writes to SRAM take place when both S-CS1# and S-WE# are low and S-OE# and S-SC2 are high. Commands are written to the flash memory's Command User Interface (CUI) using standard microprocessor write timings to control flash operations. The CUI does not occupy an addressable memory location within the flash component. The address and data buses are latched on the rising edge of the second F-WE# or F-CE# pulse, whichever occurs first. (See Figure 6 and Figure 7 for read and write waveforms.)
3.0
Flash Memory Modes of Operation
The flash memory has four read modes: read array, read configuration, read status, and read query. The write modes are program and erase. Three additional modes (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are reached using the commands summarized in Table 5, "Flash Memory Command Definitions" on page 11.
3.1
Read Array (FFH)
When F-RP# transitions from VIL (reset) to VIH, the device defaults to read array mode and will respond to the read control inputs without any additional CUI commands. In addition, the address of the desired location must be applied to the address balls. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place.
3.2
Read Identifier (90H)
The read configuration mode outputs the manufacturer/device identifier. The device is switched to this mode by writing the read configuration command (90H). Once in this mode, read cycles from addresses shown in Table 4, "Read Configuration Table" on page 8 retrieve the specified information. To return to read array mode, write the Read Array command (FFH).
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The Read Configuration mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. The device is switched to this mode by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses shown in Table 4 retrieve the specified information. To return to read array mode, write the Read Array command (FFH). Table 4. Read Configuration Table
Item Manufacturer Code (x16) Device ID (See Appendix D) Block Lock Configuration
(1)
Address 00000 00001 XX002
(2)
Data 0089 ID LOCK DQ0 = 0 DQ0 = 1 DQ1 = 1
* * *
Block Is Unlocked Block Is Locked Block Is Locked-Down
3
Protection Register Lock
80 81-88
PR-LK PR
Protection Register (x16)
NOTES: 1. See Section 3.7 for valid lock status outputs. 2. "XX" specifies the block address of lock configuration being read. 3. See Section 3.8 for protection register information. 4. Other locations within the configuration address space are reserved by Intel for future use.
3.3
Read Status Register (70H)
The status register indicates the status of device operations, and the success/failure of that operation. The Read Status Register (70H) command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the array, issue a Read Array (FFH) command. The status register bits are output on DQ0-DQ7. The upper byte, DQ8-DQ15, outputs 00H during a Read Status Register command. The contents of the status register are latched on the falling edge of F-OE# or F-CE#, whichever occurs last. This prevents possible bus errors which might occur if status register contents change while being read. F-CE# or F-OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the desired operation (see Table 6, "Flash Memory Status Register Definition" on page 12).
3.3.1
Clear Status Register (50H)
The WSM sets status bits 1 through 7 to "1," and clears bits 2, 6 and 7 to "0," but cannot clear status bits 1 or 3 through 5 to "0." Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared through the use of the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the
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status register before beginning another command or sequence. Note that the Read Array command must be issued before data can be read from the memory array. Resetting the device also clears the status register.
3.4
Read Query (98H)
The read query mode outputs Common Flash Interface (CFI) data when the device is read. This can be accessed by writing the Read Query Command (98H). The CFI data structure contains information such as block size, density, command set and electrical specifications. Once in this mode, read cycles from addresses shown in Appendix B retrieve the specified information. To return to read array mode, write the Read Array command (FFH).
3.5
Word Program (40H/10H)
Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to program desired bits of the addressed location, then verify the bits are sufficiently programmed. Programming the memory results in specific bits within an address location being changed to a "0." If the user attempts to program "1"s, the memory cell contents do not change and no error occurs. The status register indicates programming status: while the program sequence executes, status bit 7 is "0." The status register can be polled by toggling either F-CE# or F-OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the program status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then F-VPP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted on a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode.
3.5.1
Suspending and Resuming Program (B0H/D0H)
The Program Suspend command halts an in-progress program operation so that data can be read from other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to "1"). tWHRH1/ tEHRH1 specify the program suspend latency. A Read Array command can be written to the CUI to read data from any block other than the suspended block. The only other valid commands, while program is suspended, are Read Status Register, Read Configuration, Read Query, and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the programming process and status register bits SR.2 and SR.7 will automatically be cleared. The device automatically
Preliminary
9
28F1602C3, 28F1604C3, 28F3204C3
outputs status register data when read (see Appendix A, Program Suspend/Resume Flowcharts) after the Program Resume command is written. F-VPP must remain at the same F-VPP level used for program while in program suspend mode. F-RP# must also remain at VIH.
3.6
Block Erase (20H)
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to program all bits within the block to "0," erase all bits within the block to "1," then verify that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is a "0." When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase failure. If F-VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that F-VPP supply voltage was not within acceptable limits. After an erase operation, clear the status register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to place the flash in read array mode after the erase is complete.
3.6.1
Suspending and Resuming Erase (B0H/D0H)
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI suspends the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended. Erase suspend latency is specified by tWHRH2/tEHRH2. A Read Array/Program command can now be written to the CUI to read/program data from/to blocks other than that which is suspended. This nested Program command can subsequently be suspended to read yet another location. The only valid commands while erase is suspended are Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block and Lock-Down Block. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking F-CE# to VIH. This reduces active current consumption. Erase Resume continues the erase sequence when F-CE# = VIL. As with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued.
10
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Table 5.
Flash Memory Command Definitions
First Bus Cycle Second Bus Cycle Data FFH 90H 98H 70H 50H 40H/10H 20H B0H D0H 60H 60H 60H C0H C0H Write Write Write Write Write BA BA BA PA PA 01H D0H 2FH PD FFFD Write Write PA BA PD D0H Read Read Read IA QA X ID QD SRD Operation Address Data Note Operation Address X X X X X X X X X X X X X X BA = Block Address 1 1, 2 1, 2 1 1 1, 3 1 1 1 1 1, 4 1 1 1 Write Write Write Write Write Write Write Write Write Write Write Write Write Write
Command Read Array Read Identifier Read Query Read Status Register Clear Status Register Word Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Register Program Lock Protection Register X = Don't Care SRD = Status Register Data
PA = Program Address PD = Program Data
IA = Identifier Address ID = Identifier Data
QA = Query Address QD = Query Data
NOTES: 1. When writing commands, the upper data bus [DQ8-DQ15] should be either VIL or VIH, to minimize current draw. 2. Following the Read Configuration or Read Query commands, read operations output device configuration or CFI query information, respectively. 3. Either 40H or 10H command is valid, but the Intel standard is 40H. 4. When unlocking a block, WP# must be held for three clock cycles (1 clock cycle after the second command bus cycle).
Preliminary
11
28F1602C3, 28F1604C3, 28F3204C3
Table 6.
WSMS 7
Flash Memory Status Register Definition
ESS 6 ES 5 PS 4 VPPS 3 PSS 2 NOTES: BLS 1 R 0
SR.7 WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error In Block Erase 0 = Successful Block Erase SR.4 = PROGRAM STATUS (PS) 1 = Error in Programming 0 = Successful Programming SR.3 = F-VPP STATUS (VPPS) 1 = F-VPP Low Detect, Operation Abort 0 = F-VPP OK
Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1," WSM has applied the max. number of erase pulses and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word/byte. The F-VPP status bit does not provide continuous indication of VPP level. The WSM interrogates F-VPP level only after the Program or Erase command sequences have been entered, and informs the system if F-VPP has not been switched on. The F-VPP is also checked before the operation is verified by the WSM. The F-VPP status bit is not guaranteed to report accurate feedback between VPPLK and VPP1 min. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a Program Resume command is issued. If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the status register. Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits.
SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR.1 = BLOCK LOCK STATUS 1 = Prog/Erase attempted on a locked block; Operation aborted. 0 = No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy
NOTE: A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
3.7
Instant, Individual Block Locking
The instant, individual block locking feature that allows any flash block to be locked or unlocked with no latency, which enables instant code and data protection. This locking offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term "state [XYZ]" will be used to specify locking states; e.g., "state [001]," where X = value of WP#, Y = bit DQ1 of the Block Lock status register, and Z = bit DQ0 of the Block Lock status register. Table 8, "Block Locking State Transitions" on page 15 defines all of these possible locking states.
12
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
3.7.1
Block Locking Operation Summary
The following concisely summarizes the locking functionality. All blocks are locked when powered-up, and can be unlocked or locked with the Unlock and Lock commands.
* The Lock-Down command locks a block and prevents it from being unlocked when WP# = 0. * When WP# = 1, Lock-Down is overridden and commands can unlock/lock locked-down
blocks.
* When WP# returns to 0, locked-down blocks return to Lock-Down. * Lock-Down is cleared only when the device is reset or powered-down.
The locking status of each block can set to Locked, Unlocked, and Lock-Down, each of which will be described in the following sections. A comprehensive state table for the locking functions is shown in Table 8 on page 15, and a flowchart for locking operations is shown in Figure 19 on page 43.
3.7.2
Locked State
The default status of all blocks upon power-up or reset is locked (states [001] or [101]). Locked blocks are fully protected from alteration. Any program or erase operations attempted on a locked block will return an error on bit SR.1 of the status register. The status of a locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. Unlocked blocks can be locked issuing the "Lock" command sequence, 60H followed by 01H.
3.7.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the Locked state when the device is reset or powered down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate software commands. A Locked block can be unlocked by writing the Unlock command sequence, 60H followed by D0H.
3.7.4
Lock-Down State
Blocks that are Locked-Down (state [011]) are protected from program and erase operations (just like Locked blocks), but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-down by writing the Lock-Down command sequence, 60H followed by 2FH. Locked-Down blocks revert to the Locked state when the device is reset or powered down. The Lock-Down function is dependent on the WP# input ball. When WP# = 0, blocks in LockDown [011] are protected from program, erase, and lock status changes. When WP# = 1, the LockDown function is disabled ([111]) and locked-down blocks can be individually unlocked by software command to the [110] state, where they can be erased and programmed. These blocks can then be re-locked [111] and unlocked [110] as desired while WP# remains high. When WP# goes low, blocks that were previously locked-down return to the Lock-Down state [011] regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in Lock-Down, to Locked state.
Preliminary
13
28F1602C3, 28F1604C3, 28F3204C3
3.7.5
Reading a Block's Lock Status
The lock status of every block can be read in the configuration read mode of the device. To enter this mode, write 90H to the device. Subsequent reads at Block Address + 00002 will output the lock status of that block. The lock status is represented by the least significant outputs, DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates LockDown status and is set by the Lock-Down command. It cannot be cleared by software, only by device reset or power-down.
Table 7.
Block Lock Status
Item Block Lock Configuration * Block Is Unlocked * Block Is Locked * Block Is Locked-Down Address XX002 Data LOCK DQ0 = 0 DQ0 = 1 DQ1 = 1
3.7.6
Locking Operation during Erase Suspend
Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the erase suspend command (B0H), then check the status register until it indicates that the erase operation has been suspended. Next write the desired lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command (D0H). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend.
3.7.7
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Since locking changes are performed using a two cycle command sequence, e.g., 60H followed by 01H to lock a block, following the Configuration Setup command (60H) with an invalid command will produce a lock command error (SR.4 and SR.5 will be set to 1) in the status register. If a lock command error occurs during an erase suspend, SR.4 and SR.5 will be set to 1, and will remain at 1 after the erase is resumed. When erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an erase suspend.
14
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Table 8.
Block Locking State Transitions
Erase/ Program Allowed? Yes Yes No No No Yes No Next State after Command Input Lock Go To [001] Go To [101] - - - Go To [111] Unlock - - Go To [000] Go To [100] - - Go To [110] Lock-Down Go To [011] Go To [111] Go To [011] Go To [111] - Go To [111] -
Current State WP# 0 1 0 1 0 1 1 DQ1 0 0 0 0 1 1 1 DQ0 0 0 1 1 1 0 1 Name Unlocked Unlocked Locked (Default) Locked Locked-Down Lock-Down Disabled
NOTES: 1. "-" indicates no change in the current state. 2. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ1, and Z = DQ0. The current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ0, DQ1). DQ0 indicates if a block is locked (1) or unlocked (0). DQ1 indicates if a block has been lockeddown (1) or not (0). 3. At power-up or device reset, all blocks default to Locked state [001] (if WP# = 0). Holding WP# = 0 is the recommended default. 4. The "Erase/Program Allowed?" column shows whether erase and program operations are enabled (Yes) or disabled (No) in that block's current locking state. 5. The "Lock Command Input Result [Next State]" column shows the result of writing the three locking commands (Lock, Unlock, Lock-Down) in the current locking state. For example, "Goes To [001]" would mean that writing the command to a block in the current locking state would change it to [001]. 6. The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designs to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming.
3.8
128-Bit Protection Register
The 3 Volt Advanced+ Stacked-CSP architecture includes a 128-bit protection register than can be used to increase the security of a system design. For example, the number contained in the protection register can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution.
3.8.1
Reading the Protection Register
The protection register is read in the configuration read mode. The device is switched to this mode by writing the Read Configuration command (90H). Once in this mode, read cycles from addresses shown in Appendix E retrieve the specified information. To return to read array mode, write the Read Array command (FFH).
3.8.2
Programming the Protection Register (C0H)
The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide parts. First write the Protection Program Setup command, C0H. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Appendix E. See Figure 20, "Protection Register Programming Flowchart" on page 44.
Preliminary
15
28F1602C3, 28F1604C3, 28F3204C3
Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error (program error bit SR.4 will be set to 1). Attempting to program or to a previously locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR.1 will be set to 1).
3.8.3
Locking the Protection Register
The user-programmable segment of the protection register is lockable by programming Bit 1 of the PR-LOCK location to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. This bit is set using the Protection Program command to program FFFDH to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. A Protection Program command to locked words will result in a status register error (program error bit SR.4 and Lock Error bit SR.1 will be set to 1). The protection register lockout state is not reversible.
Figure 3. Protection Register Memory Map
88H 4 Words User Programmed 85H 84H 4 Words Factory Programmed 81H 80H PR-LOCK
0645_05
3.9
Additional Flash Features
Intel 3 Volt Advanced+ Stacked-CSP products provide in-system programming and erase in the 1.65 V-3.3 V range. For fast production programming, it also includes a low-cost, backwardcompatible 12 V programming feature.
3.9.1
Improved 12 Volt Production Programming
When F-VPP is between 1.65 V and 3.3 V, all program and erase current is drawn through the F-VCC signal. Note that if F-VPP is driven by a logic signal, VIH min = 1.65 V. That is, F-VPP must remain above 1.65 V to perform in-system flash modifications. When F-VPP is connected to a 12 V power supply, the device draws program and erase current directly from the F-VPP signal. This eliminates the need for an external switching transistor to control the voltage F-VPP. Figure 12, "Example Power Supply Configurations" on page 34 shows examples of how the flash power supplies can be configured for various usage models.
16
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
The 12 V F-VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12 V may be applied to F-VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
3.9.2
F-VPP VPPLK for Complete Protection
In addition to the flexible block locking, the F-VPP programming voltage can be held low for absolute hardware write protection of all blocks in the flash device. When F-VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding status register bit (SR.3) to be set.
4.0
4.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Extended Operating Temperature During Read During Flash Block Erase and Program Temperature under Bias Storage Temperature Voltage on Any Ball (except F-VCC / S-VCC and F-VPP) with Respect to GND F-VPP Voltage (for BLock Erase and Program) with Respect to GND F-VCC / F-VCCQ / S-VCC Supply Voltage with Respect to GND Output Short Circuit Current -65C to +125C -0.5 V to +3.3 V(1) -0.5 V to +13.5 V(1,2,4) -0.2V to +3.3 V 100 mA(3) -40C to +85C Maximum Rating
NOTES: 1. Minimum DC voltage is -0.5 V on input/output balls. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output balls is F-VCC / F-VCCQ / S-VCC + 0.5 V which, during transitions, may overshoot to F-VCC / F-VCCQ / S-VCC + 2.0 V for periods < 20 ns. 2. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. F-VPP voltage is normally 1.65 V-3.3 V. Connection to supply of 11.4 V-12.6 V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.9.1 for details.
NOTICE: This datasheet contains information on products in full production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Preliminary
17
28F1602C3, 28F1604C3, 28F3204C3
4.2
Table 9.
Operating Conditions
Temperature and Voltage Operating Conditions
Symbol TA VCC / VCCQ VPP1 VPP2 Cycling Block Erase Cycling Parameter Operating Temperature F-VCC/S-VCC Supply Voltage Supply Voltage 1 1 1, 2 2 Notes Min -40 2.7 1.65 11.4 1,000,000 Max +85 3.3 3.3 12.6 Units C Volts Volts Volts Cycles
NOTES: 1. F-VCC/F-VCCQ must share the same supply. F-VCC/S-VCC must share the same supply when not in data retention. 2. Applying F-VPP = 11.4 V-12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.9.1 for details.
4.3
Capacitance
TA = +25C, f = 1 MHz
Sym CIN COUT Parameter Input Capacitance Output Capacitance Notes 1 1 Typ 16 20 Max 18 22 Units pF pF Conditions VIN = 0 V VOUT = 0 V
NOTE: 1. Sampled, not 100% tested.
18
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
4.4
DC Characteristics
2.7 V - 3.3 V
Symbol
Parameter
Device
Note Typ Max 2 0.2 10
Unit
Test Conditions F-VCC/S-VCC = VCC1 Max VIN = VCC1 Max or GND F-VCC/S-VCC = VCC1 Max VIN = VCC1 Max or GND F-VCC = VCC1 Max F-CE# = F-RP# = VCC1 F-WP# = VCC1 or GND VIN = VCC1 Max or GND S-VCC = VCC1 Max S-CS#1 = VCC, S-CS2 = VCC or S-CS2 = GND VIN = VCC1 Max or GND F-VCC = VCCMax VIN = VCC1 Max or GND F-RP# = GND 0.2 V
ILI ILO
Input Load Current Output Leakage Current
Flash/ SRAM Flash/ SRAM
1,7 1,7
A A
Flash ICCS VCC Standby Current
1
10
25
A
2-Mb SRAM 4-Mb SRAM
1 1
-
10 20
A A
ICCD
VCC Deep Power-Down Current
Flash 2-Mb SRAM 4-Mb SRAM 2-Mb SRAM 4-Mb SRAM
1,7
7
25
A
1 1 1 1
-
7 10 40 45
mA mA mA mA
ICC
Operating Power Supply Current (cycle time = 1 s)
IIO = 0 mA, S-CS#1 = VIL S-CS2 = S-WE# = VIH VIN = VIL or VIH Cycle time = Min, 100% duty, IIO = 0 mA, S-CS#1 = VIL, S-CS2 = VIH, VIN = VIL or VIH F-VCC = VCC1Max
ICC2
Operating Power Supply Current (min cycle time)
ICCR
VCC Read Current
Flash
1,5,7
9
18
mA
F-OE# = VIH, F-CE# = VIL f = 5 MHz, IOUT = 0 mA VIN = VIL or VIH F-VPP = VPP1 Program in Progress F-VPP = VPP2 (12 V) Program in Progress F-VPP = VPP1 Erase in Progress F-VPP = VPP2 (12 V) Erase in Progress F-CE# = VCC, Erase Suspend in Progress F-CE# = VCC, Program Suspend in Progress F-RP# = GND 0.2 V F-VPP VCC1
Flash ICCW VCC Program Current
1,4
18 8
55 15 45 15 25 25 5
mA mA mA mA A A A
Flash ICCE VCC Erase Current
1,4
16 8
ICCES ICCWS IPPD
VCC Erase Suspend Current VCC Program Suspend Current F-VPP Deep Power-Down Current
Flash Flash Flash
1,2,4 1,2,4 1
10 10 0.2
Preliminary
19
28F1602C3, 28F1604C3, 28F3204C3
DC Characteristics, Continued
2.7 V - 3.3 V Symbol IPPS IPPR Parameter F-VPP Standby Current F-VPP Read Current Device Flash Flash 1,4 50 0.05 IPPW F-VPP Program Current Flash 1,4 8 0.05 IPPE F-VPP Erase Current Flash 1,4 8 0.2 IPPES F-VPP Erase Suspend Current Flash 1,4 50 0.2 IPPWS F-VPP Program Suspend Current Flash 1,4 50 200 A 200 5 A A F-VPP = VPP2 (12 V) Erase Suspend in Progress F-VPP = VPP1 Program Suspend in Progress F-VPP = VPP2 (12 V) Program Suspend in Progress 22 5 mA A F-VPP = VPP2 (12 V) Program in Progress F-VPP = VPP1 Erase Suspend in Progress 22 0.1 mA mA F-VPP = VPP2 (12 V) Program in Progress F-VPP = VPP1 Program in Progress Note Typ 1 1 0.2 2 Max 5 15 200 0.1 A A A mA F-VPP VCC1 F-VPP VCC1 F-VPP VCC1 F-VPP =VPP1 Program in Progress Unit Test Conditions
20
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
DC Characteristics, Continued
2.7 V - 3.3 V Symbol Parameter Device Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash Flash 7 7 3 3 3,6 Flash 1.65 11.4 1.5 Note Min VIL VIH VOL VOH VPPLK VPP1 VPP2 VLKO Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage F-VPP Lock-Out Voltage F-VPP during Program / Erase Operations VCC Prog/Erase Lock Voltage -0.2 2.2 -0.10 VCC - 0.1 1.0 3.3 12.6 V Max 0.6 VCC +0.2 0.10 V V V V V V F-VCC/S-VCC = VCC1 Min IOL = 100 A F-VCC/S-VCC = VCC1 Min IOH = -100 A Complete Write Protection Unit Test Conditions
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal F-VCC/S-VCC, TA = +25 C. 2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR. 3. Erase and Program are inhibited when F-VPP < VPPLK and not guaranteed outside the valid F-VPP ranges of VPP1 and VPP2. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 6. Applying F-VPP = 11.4 V-12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. F-VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.9.1 for details.
Preliminary
21
28F1602C3, 28F1604C3, 28F3204C3
Figure 4. Input/Output Reference Waveform
VCC INPUT 0.0
0645_07
VCC 2
TEST POINTS
VCC 2
OUTPUT
NOTE: AC test inputs are driven at VCCQ for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10%-90%) <10 ns. Worst case speed conditions are when VCCQ = VCCQMin.
Figure 5. Test Configuration
VCCQ R1 Device Under Test Out CL R2
0666_05
NOTE: CL includes jig capacitance.
Flash Test Configuration Component Values Table
Test Configuration 2.7 V-3.3 V Standard Test CL (pF) 50 R1 () 25K R2 () 25K
22
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
4.5
Flash AC Characteristics--Read Operations
Density Product -90 16 Mbit -110 -100 32 Mbit -110 Unit Voltage Range Note Min 90 90 2 2 90 30 150 3 3 3 3 3 0 0 0 25 20 0 0 0 25 20 0 Max Min 110 110 110 30 150 0 0 25 20 0 2.7 V - 3.3 V Max Min 100 100 100 30 150 0 0 25 20 Max Min 110 110 110 30 150 Max ns ns ns ns ns ns ns ns ns ns
#
Sym
Parameter
R1 R2 R3 R4 R5 R6 R7 R8 R9
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address to Output Delay F-CE# to Output Delay F-OE# to Output Delay F-RP# to Output Delay F-CE# to Output in Low Z F-OE# to Output in Low Z F-CE# to Output in High Z F-OE# to Output in High Z Output Hold from Address, F-CE#, or F-OE# Change, Whichever Occurs First
R10 tOH
NOTES: 1. See Figure 6, below. 2. F-OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, but not 100% tested. 4. See Figure 4, "Input/Output Reference Waveform" on page 22 for timing measurements and maximum allowable input slew rate.
Figure 6. AC Waveform: Flash Read Operations
Device and Address Selection Address Stable R1 Data Valid
VIH ADDRESSES (A) VIL CE# (E) VIH VIL VIH OE# (G) VIL VIH WE# (W) VIL VOH DATA (D/Q) VOL RP#(P) VIH VIL High Z
Standby
R8
R9 R7 R6 R2 R5 R4 R3 Valid Output High Z R10
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
4.6
Flash AC Characteristics--Write Operations
Density Product 16 Mbit -90 -110 32 Mbit -100 -110 Unit Voltage Range Note Min 150 0 4 2 2 60 50 60 0 2 2 4 3 3 0 0 30 200 0 2.7 V - 3.3 V Max 150 0 70 60 70 0 0 0 30 200 0 Min 150 0 70 60 70 0 0 0 30 200 0 Max 150 0 70 60 70 0 0 0 30 200 0 ns ns ns ns ns ns ns ns ns ns ns
#
Sym
Parameter
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11
tPHWL / tPHEL tELWL tWLEL tELEH tWLWH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL
F-RP# High Recovery to F-WE# (F-CE#) Going Low F-CE# (F-WE#) Setup to F-WE# (F-CE#) Going Low F-WE# (F-CE#) Pulse Width Data Setup to F-WE# (F-CE#) Going High Address Setup to F-WE# (F-CE#) Going High F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High Data Hold Time from F-WE# (F-CE#) High Address Hold Time from F-WE# (F-CE#) High F-WE# (F-CE#) Pulse Width High F-VPP Setup to F-WE# (F-CE#) Going High F-VPP Hold from Valid SRD
NOTES: 1. Write timing characteristics during erase suspend are the same as during write-only operations. 2. Refer to Table 5, "Flash Memory Command Definitions" on page 11 for valid AIN or DIN. 3. Sampled, but not 100% tested. 4. Write pulse width (tWP) is defined from F-CE# or F-WE# going low (whichever goes low last) to F-CE# or F-WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from F-CE# or F-WE# going high (whichever goes high first) to F-CE# or F-WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 5. See Figure 4, "Input/Output Reference Waveform" on page 22 for timing measurements and maximum allowable input slew rate. 6. See Figure 7, "AC Waveform: Flash Program and Erase Operations" on page 26.
24
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
4.7
Flash Erase and Program Timings(1)
F-VPP 1.65 V- 3.3 V Typ(1) 0.10 0.8 22 0.5 1 5 5 Max 0.30 2.4 200 4 5 10 20 11.4 V- 12.6 V Unit Note Typ(1) 0.03 0.24 8 0.4 0.6 5 5 Max 0.12 1 185 4 5 10 20 s s s s s s s 2, 3 2, 3 2, 3 2, 3 2, 3 3 3
Symbol tBWPB tBWMB tWHQV1 / tEHQV1 tWHQV2 / tEHQV2 tWHQV3 / tEHQV3 tWHRH1 / tEHRH1 tWHRH2 / tEHRH2
Parameter 4-KW Parameter Block Program Time (Word) 32-KW Main Block Program Time (Word) Word Program Time 4-KW Parameter Block Erase Time (Word) 32-KW Main Block Erase Time (Word) Program Suspend Latency Erase Suspend Latency
NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested.
Preliminary
25
28F1602C3, 28F1604C3, 28F3204C3
Figure 7. AC Waveform: Flash Program and Erase Operations
VIH
ADDRESSES [A]
A
B AIN
C AIN W5 W6 W9 W8
D
E
F
VIL VIH
CE#(WE#) [E(W)]
(Note 1)
VIL VIH W2
OE# [G]
VIL VIH
WE#(CE#) [W(E)]
(Note 1)
VIL VIH
DATA [D/Q]
W3 W4
High Z
W7 DIN DIN
VIL
W1
Valid SRD
DIN
RP# [P]
VIH VIL VIH
WP#
VIL VPPH 2 VPPH1 VPPLK VIL
W10
W11
V
PP
[V]
NOTES: 1. F-CE# must be toggled low when reading Status Register Data. F-WE# must be inactive (high) when reading Status Register Data. A. F-VCC Power-Up and Standby. B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F. Write Read Array Command.
26
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
4.8
Flash Reset Operations
Figure 8. AC Waveform: Reset Operation
RP# (P)
VIH VIL
t PLPH (A) Reset during Read Mode
t PHQV t PHWL t PHEL
Abort Complete
t PLRH
RP# (P)
VIH V IL
t PHQV t PHWL t PHEL
t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH
Abort Deep Complete PowerDown
RP# (P)
VIH V IL
t PLRH
t PHQV t PHWL t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
Table 10. Reset Specifications(1)
F-VCC 2.7 V - 3.3 V Symbol Parameter F-RP# Low to Reset during Read (If F-RP# is tied to VCC, this specification is not applicable) F-RP# Low to Reset during Block Erase F-RP# Low to Reset during Program Note Min tPLPH tPLRH1 tPLRH2 2,4 3,4 3,4 100 22 12 Max ns s s Unit
NOTES: 1. See Section 2.1.4 for a full description of these conditions. 2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed. 3. If F-RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns. 4. Sampled, but not 100% tested.
Preliminary
27
28F1602C3, 28F1604C3, 28F3204C3
4.9
SRAM AC Characteristics--Read Operations(1,4)
Density # Sym Parameter Voltage Range Note R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH tBLZ tBHZ Read Cycle Time Address to Output Delay S-CS1#, S-CS2 to Output Delay S-OE# to Output Delay S-UB#, LB# to Output Delay S-CS1#, S-CS2 to Output in Low Z S-OE# to Output in Low Z S-CS1#, S-CS2 to Output in High Z S-OE# to Output in High Z Output Hold from Address, S-CS1#, S-CS2, or S-OE# Change, Whichever Occurs First S-UB#, S-LB# to Output in Low Z S-UB#, S-LB# to Output in High Z 2, 3 2 3 2/4 Mbit 2.7 V- 3.3 V Min 70 - - - - 5 0 0 0 0 0 0 Max - 70 70 35 70 - - 25 25 - - 25 ns ns ns ns ns ns ns ns ns ns ns ns Unit
NOTE: 1. See Figure 9, "AC Waveform: SRAM Read Operations" on page 29. 2. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 3. At any given temperature and voltage condition, tHZ (Max) is less than and tLZ (Max) both for a given device and from device to device interconnection. 4. Sampled, but not 100% tested.
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Figure 9. AC Waveform: SRAM Read Operations
Device Address Selection Address Stable VIL VIH R1
Standby VIH
Data Valid
ADDRESSES (A)
CS1# (E1) CS2 (E2)
VIL VIH VIL R2 VIH VIL R9 R4 VIL R7 High Z R6 Valid Output R11 R5 R12 R10 High Z VOH VOL VIH VIH R3 R8
OE# (G)
WE# (W)
VIH
DATA (D/Q)
UB#, LB#
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
4.10
SRAM AC Characteristics--Write Operations(1, 2)
Density # Sym Parameter Volt Note W1 W2 W3 W4 W5 W6 W7 W8 W9 tWC tAS tWP tDW tAW tCW tDH tWR tBW Write Cycle Time Address Setup to S-WE# (S-CS1#) and S-UB#, S-LB# Going Low S-WE# (S-CS1#) Pulse Width Data to Write Time Overlap Address Setup to S-WE# (S-CS1#) Going High S-CE# (S-WE#) Setup to S-WE# (S-CS1#) Going High Data Hold Time from S-WE# (S-CS1#) High Write Recovery S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going High 5 4 3 2/4 Mbit 2.7 V - 3.3 V Min 70 0 55 30 60 60 0 0 60 Max - - - - - - - - - ns ns ns ns ns ns ns ns ns Unit
NOTES: 1. See Figure 10, "AC Waveform: SRAM Write Operations" on page 31. 2. A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1# goes low and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or simultaneously asserting S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS1# goes high and S-WE# goes high. The tWP is measured from the beginning of write to the end of write. 3. tWP is measured from S-CS1# going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or S-WE# going high.
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Figure 10. AC Waveform: SRAM Write Operations
Device Address Selection Address Stable VIL VIH W1 W8
Standby VIH
ADDRESSES (A)
CS1# (E1) CS2 (E2)
VIL VIH VIL VIH VIL W5 W3 W6
OE# (G)
WE# (W)
VIH VIL
W7 W4 High Z High Z
DATA (D/Q)
VOH VOL
Data In W9
W2 VIH
UB#, LB#
VIH
4.11
SRAM Data Retention Characteristics(1) --Extended Temperature
Parameter S-VCC for Data Retention Deep Retention Current Data Retention Set-up Time Recovery Time Note 2 2 Min 1.5 - 0 tRC Typ - - - - Max 3.3 5 - - Unit V A ns ns Test Conditions CS1# VCC1 - 0.2 V S-VCC = 1.5 V CS1# VCC1 - 0.2 V See Data Retention Waveform
Sym VDR IDR tSDR tRDR
NOTES: 1. Typical values at nominal S-VCC, TA = +25 C. 2. S-CS1# VCC1 - 0.2 V, S-CS2 VCC1 - 0.2 V (S-CS1# controlled) or S-CS2 0.2 V (S-CS2 controlled).
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Figure 11. SRAM Data Retention Waveform
tSDR Data Retention Mode tRDR
CS1# Controlled VCC 3.0/2.7V
CS1# (E1) 2.2V
VDR GND CS2 Controlled tSDR VCC 3.0/2.7V Data Retention Mode tRDR
CS2 (E2)
VDR 0.4V GND
5.0
Migration Guide Information
Typically, it is important to discuss footprint migration compatibility between a new product and existing products. In this specific case, the Stacked CSP allows the system designer to remove two separate memory footprints for individual flash and SRAM and replace them with a single footprint, thus resulting in an overall reduction in board space required. This implies that a new printed circuit board would be used to take advantage of this feature. Since the flash in Stacked-CSP shares the same features as the Advanced+ Boot Block Features, conversions from the Advanced Boot Block are described in AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory, order number 292216. Please contact your local Intel representation for detailed information about specific Flash + SRAM system migrations.
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28F1602C3, 28F1604C3, 28F3204C3
6.0
System Design Considerations
This section contains information that would have been contained in a product design guide in earlier generations. In an effort to simplify the amount of documentation, relevant system design considerations have been combined into this document.
6.1
Background
The Intel Advanced+ Boot Block Stacked chip scale package combines the features of the Advanced+ Boot Block flash memory architecture with a low-power SRAM to achieve an overall reduction in system board space. This enables applications to integrate security with simple software and hardware configurations, while also combining the system SRAM and flash into one common footprint. This section discusses how to take full advantage of the 3 Volt Advanced+ Boot Block Stacked Chip Scale Package.
6.1.1
Flash + SRAM Footprint Integration
The Stacked Chip Scale Package memory solution can be used to replace a subset of the memory subsystem within a design. Where a previous design may have used two separate footprints for SRAM and Flash, you can now replace with the industry-standard I-ballout of the Stacked CSP device. This allows for an overall reduction in board space, which allows the design to integrate both the flash and the SRAM into one component.
6.1.2
Advanced+ Boot Block Flash Memory Features
Advanced+ Boot Block adds the following new features to Intel Advanced Boot Block architecture:
* Instant, individual block locking provides software/hardware controlled, independent locking/
unlocking of any block with zero latency to protect code and data.
* A 128-bit Protection Register enables system security implementations. * Improved 12 V production programming simplifies the system configuration required to
implement 12 V fast programming.
* Common Flash Interface (CFI) provides component information on the chip to allow softwareindependent device upgrades. For more information on specific advantages of the Advanced+ Boot Block Flash Memory, please see AP-658 Designing with the Advanced+ Boot Block Flash Memory Architecture.
6.2
Flash Control Considerations
The flash device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, F-VPP or F-VCC, powers-up first. Example flash power supply configurations are shown in Figure 12, "Example Power Supply Configurations" on page 34.
Preliminary
33
28F1602C3, 28F1604C3, 28F3204C3
6.2.1
F-RP# Connected to System Reset
The use of F-RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting F-RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when F-VCC voltages are above VLKO. Since both F-WE# and F-CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until F-RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
6.2.2
F-VCC, F-VPP and F-RP# Transition
The CUI latches commands as issued by system software and is not altered by F-VPP or F-CE# transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after F-VCC transitions above VLKO (Lockout voltage), is read array mode. After any program or block erase operation is complete (even after F-VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
Figure 12. Example Power Supply Configurations
System Supply
System Supply 12 V Supply 10 K 12 V Fast Programming Absolute Write Protection With V PP VPPLK System Supply
(Note 1)
VCC VPP
Prot# (Logic Signal)
VCC VPP
Low-Voltage Programming Absolute Write Protection via Logic Signal System Supply
VCC VPP
VCC VPP
Low-Voltage Programming
12 V Supply Low Voltage and 12 V Fast Programming
NOTE: 1. A resistor can be used if the F-VCC supply can sink adequate current based on resistor value.
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
6.3
Noise Reduction
Stacked-CSP memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues for both the flash and SRAM:
1. Standby current levels (ICCS) 2. Read current levels (ICCR) 3. Transient peaks produced by falling and rising edges of F-CE#, S-CS1#, and S-CS2.
Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each device should have a capacitors between individual power (F-VCC, F-VCCQ, F-VPP, SVCC)and ground (GND) signals. High-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. Noise issues within a system can cause devices to operate erratically if it is not adequately filtered. In order to avoid any noise interaction issues within a system, it is recommended that the design contain the appropriate number of decoupling capacitors in the system. Noise issues can also be reduced if leads to the device are kept very short, in order to reduce inductance. Decoupling capacitors between VCC and VSS reduce voltage spikes by supplying the extra current needed during switching. Placing these capacitors as close to the device as possible reduces line inductance. The capacitors should be low inductance capacitors; surface mount capacitors typically exhibit lower inductance. It is highly recommended that systems use a 0.1 f capacitor for each of the D9, D10, A10 and E4 grid ballout locations (see Figure 1 for ballout). These capacitors are necessary to avoid undesired conditions created by excess noise. Smaller capacitors can be used to decouple higher frequencies.
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Figure 13. Typical Flash + SRAM Substrate Power and Ground Connections
SUBSTRATE FLASH DIE SRAM DIE S-V SSQ F-V SSQ D3 S-V SS S-V CC D9 S-V CCQ F-V CC F-V CCQ E4 F-V PP F-V SS D10 A10 A9
H8
XX S-X F-X
Substrate connection to package ball SRAM die bond pad connection Flash die bond pad connection
NOTES: 1. Substrate connections refer to ballout locations shown in Figure 1. 2. 0.1f capacitors should be used with D9, D10, A10and E4. 3. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS. 4. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a VCC.
6.4
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while also programming or erasing flash. In addition, F-CE#, S-CS1# and S-CS2 should not be enabled at the same time. (See Table 2, "3 Volt Advanced+ Stacked-CSP Ball Descriptions" on page 3 for a summary of recommended operating modes.) Simultaneous operation of the can be summarized by the following:
* SRAM read/write are during a Flash Program or Erase Operation are allowed. * Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus
contention).
6.4.1
SRAM Operation during Flash "Busy"
This functionality provides the ability to use both the flash and the SRAM "at the same time" within a system, similar to the operation of two devices with separate footprints. This operation can be achieved by following the appropriate timing constraints within a system.
36
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
6.4.2
Simultaneous Bus Operations
Operations that require both the SRAM and Flash to be in active mode are disallowed. An example of these cases would include simultaneous reads on both the flash and SRAM, which would result in contention for the data bus. Finally, a read of one device while attempting to write to the other (similar to the conditions of direct memory access (DMA) operation) are also not within the recommended operating conditions. Basically, only one memory can drive the outputs out the device at one given point in time.
6.5
Printed Circuit Board Notes
The Intel Stacked CSP will save significant space on your PCB by combining two chips into one BGA style package. Intel Stacked CSP has a 0.8 mm pitch that can be routed on your Printed Circuit Board with conventional design rules. Trace widths of 0.127 mm (0.005 inches) are typical. Unused balls in the center of the package are not populated to further increase the routing options. Standard surface mount process and equipment can be used for the Intel Stacked CSP.
Figure 14. Standard PCB Design Rules Can be Used with Stacked CSP Device
Land Pad Diameter: 0.35 mm (0.0138 in) Solder Mask Opening: 0.50 mm (0.0198 in)
Trace Width: 0.127 mm (0.005 in) Trace Spaces: 0.160 mm (0.00625 in) Via Capture Pad: 0.51 mm (0.020 in) Via Drill Size: 0.25 mm (0.010 in)
NOTE: Top View
6.6
System Design Notes Summary
The Advanced+ Boot Block Stacked CSP allows higher levels of memory component integration. Different power supply configurations can be used within the system to achieve different objectives. At least three different 0.1 f capacitors should be used to decouple the devices within a system. SRAM reads or writes during a flash program or erase are supported operations. Standard printed circuit board technology can be used.
Preliminary
37
28F1602C3, 28F1604C3, 28F3204C3
7.0
Ordering Information
RD2 8 F 1 6 0 2 C3 T 9 0
Package RD = 8x12 Ball Matrix CSP Access Speed (ns) 16 Mbit = 90, 110 32 Mbit = 110 T = Top Blocking B = Bottom Blocking Product Family C3 = 3 V Advanced+ Boot Block VCC = 2.7 V - 3.6 V VPP = 1.65 V - 3.6 V or 11.4 V - 12.6 V
Product line designator for all Intel(R) Flash products
Flash Device Density 320 = x16 (32 Mbit) 160 = x16 (16 Mbit)
SRAM Device Density 4 = x16 (4 Mbit) 2 = x16 (2 Mbit)
8.0
Additional Information
Order Number 292216 292215 Contact Your Intel Representative 297874 Document/Tool
AP-658 Designing for Upgrade to the Advanced+ Boot Block Flash Memory AP-657 Designing with the Advanced+ Boot Block Flash Memory Architecture Flash Data Integrator (FDI) Software Developer's Kit FDI Interactive: Play with Intel's Flash Data Integrator on Your PC
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools.
38
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Appendix A Program/Erase Flowcharts
Figure 15. Automated Word Programming Flowchart
Start
Bus Operation Write Write Command Program Setup Program Comments Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H
Program Address/Data
Read
Read Status Register
Standby
SR.7 = 1? Yes Full Status Check if Desired
No
Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4 = 0 1 SR.1 = 0 Program Successful
If an error is detected, clear the status register before attempting retry or other error recovery.
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = VPP Program Error Check SR.1 1 = Attempted Program to Locked Block - Program Aborted
VPP Range Error 1 Programming Error
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
Attempted Program to Locked Block - Aborted
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked.
Preliminary
39
28F1602C3, 28F1604C3, 28F3204C3
Figure 16. Program Suspend/Resume Flowchart
Start
Bus Operation Write
Command Program Suspend Read Status
Comments Data = B0H Addr = X Data = 70H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Program Suspended 0 = Program Completed
Write B0H
Write
Write 70H
Read
Read Status Register
Standby
SR.7 = 1 SR.2 = 1
0
Standby
Write
Read Array
Data = FFH Addr = X Read array data from block other than the one being programmed.
0
Program Completed
Read Program Resume
Write
Write FFH
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Program Resumed
Read Array Data
0645_13
40
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Figure 17. Automated Block Erase Flowchart
Start
Bus Operation Command Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 20H
Write
Erase Setup
Write D0H and Block Address
Write
Erase Confirm
Read
Read Status Register No
Suspend Erase Loop 0 Suspend Erase Yes
Standby
SR.7 = 1 Full Status Check if Desired
Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. Write FFH after the last write operation to reset device to read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.4,5 = 0 1 SR.5 = 0 1 SR.1 = 0 Block Erase Successful
0645_14
Bus Operation Standby
Command
Comments Check SR.3 1 = VPP Low Detect Check SR.4,5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted
VPP Range Error
Standby
1
Command Sequence Error
Standby
Standby
Block Erase Error
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Attempted Erase of Locked Block - Aborted
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Figure 18. Erase Suspend/Resume Flowchart
Start
Bus Operation Write
Command Erase Suspend Read Status
Comments Data = B0H Addr = X Data = 70H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed
Write B0H
Write
Write 70H
Read
Read Status Register
Standby
SR.7 = 1 SR.6 = 1
0
Standby
Write
Read Array
Data = FFH Addr = X Read array data from block other than the one being erased.
0
Erase Completed
Read
Write
Erase Resume
Write FFH
Data = D0H Addr = X
Read Array Data
Done Reading Yes Write D0H
No
Write FFH
Erase Resumed
Read Array Data
0645_15
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Figure 19. Locking Operations Flowchart
Bus Operation Write
Start
Command Config. Setup
Comments Data = 60H Addr = X Data= 01H (Lock Block) D0H (Unlock Block) 2FH (Lockdown Block) Addr=Within block to lock Data = 90H Addr = X Block Lock Status Data Addr = Second addr of block Confirm Locking Change on DQ1, DQ0. (See Block Locking State Table for valid combinations.)
Write 60H (Configuration Setup) Write 01H, D0H, or 2FH
Write
Lock, Unlock, or Lockdown Read Configuration Block Lock Status
Write (Optional) Read (Optional) Standby (Optional)
Write 90H (Read Configuration)
Optional
Read Block Lock Status
Locking Change Confirmed? No Write FFh (Read Array)
Locking Change Complete
0645_16
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Figure 20. Protection Register Programming Flowchart
Start
Bus Operation Write Write
Command Protection Program Setup Protection Program
Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 = 1? Yes Full Status Check if Desired
No
Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPP Range Error 0,1 SR.1, SR.4 =
Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 VPP Low 0 0 1 Prot. Reg. Prog. Error Register Locked: Aborted
1
0
1
Protection Register Programming Error Attempted Program to Locked Register Aborted
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
1,1 SR.1, SR.4 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Program Successful
0645_17
44
Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Appendix B CFI Query Structure
This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (DQ0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (DQ0-7) and 00h in the high byte (DQ8-15). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 11. Summary of Query Structure Output as a Function of Device and Mode
Device Device Address Hex Offset 10: 11: 12: Code 51 52 59 ASCII Value "Q" "R" "Y"
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Table 12. Example of Query Structure Output of x16 and x8 Devices
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Hex Code D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Value Offset A7-A0 10h 11h 12h 13h 14h 15h 16h 17h 18h ... 51 52 59 P_IDLO P_IDLO P_IDHI ... Byte Addressing Hex Code D7-D0 "Q" "R" "Y" PrVendor ID # ID # ... Value
B.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below.
Table 13. Query Structure(1)
Offset 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Manufacturer Code Device Code Block-specific information Reserved for vendor-specific information Command set ID and vendor data offset Device timing & voltage information Flash device layout Vendor-defined additional information specific to the Primary Vendor Algorithm Description
NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = The beginning location of a Block Address (e.g., 08000h is the beginning location of block 1 when the block size is 32 Kword). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table.
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
B.3
Block Lock Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Block Erase Status (BSR.1) allows system software to determine the success of the last block erase operation. BSR.1 can be used just after power-up to verify that the VCC supply was not accidentally removed during an erase operation. This bit is only reset by issuing another erase operation to the block. The Block Status Register is accessed from word address 02h within each block.
Table 14. Block Status Register
Offset (BA+2)h
(1)
Length 1
Description Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR.1 Block Lock-Down Status 0 = Not locked down 1 = Locked down BSR 2-7: Reserved for future use
Address BA+2: BA+2:
Value --00 or --01 (bit 0): 0 or 1
BA+2: BA+2:
(bit 1): 0 or 1 (bit 2-7): 0
NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 15. CFI Identification
Offset 10h Length 3 Description Query-unique ASCII string "QRY" Addr. 10 11: 12: 13: 14: 15: 16: 17: 18: 19: 1A: Hex Code --51 --52 --59 --03 --00 --35 --00 --00 --00 --00 --00 Value "Q" "R" "Y"
13h 15h 17h 19h
2 2 2 2
Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
B.5
System Interface Information
Table 16. System Interface Information
Offset 1Bh Length 1 Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2n ms "n" such that typical full chip erase time-out = 2n ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2n times typical "n" such that maximum chip erase time-out = 2n times typical Addr. 1B: Hex Code --27 Value 2.7 V
1Ch
1
1C:
--36
3.6 V
1Dh
1
1D:
--B4
11.4 V
1Eh 1Fh 1Bh
1 1 1
1E: 1F: 1B:
--C6 --05 --27
12.6 V 32 s 2.7 V
1Ch
1
1C:
--36
3.6 V
1Dh
1
1D:
--B4
11.4 V
1Eh 1Fh 1Bh
1 1 1
1E: 1F: 1B:
--C6 --05 --27
12.6 V 32 s 2.7 V
1Ch
1
1C:
--36
3.6 V
1Dh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1
1D: 20: 21: 22: 23: 24: 25: 26:
--B4 --00 --0A --00 --04 --00 --03 --00
11.4 V n/a 1s n/a 512 s n/a 8s NA
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
B.6
n
Device Geometry Definition
Table 17. Device Geometry Definition
Offset 27h 28h 2Ah Length 1 2 2 Description "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2Ch 1 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 2Dh 4 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 2D: 2E: 2F: 30: 31: 32: 33: 34: 2C: --02 2 27: 28: 29: 2A: 2B: Code See Table Below --01 --00 --00 --00 x16 0
31h
4
Device Geometry Definition 16 Mbit Address -B 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: --15 --01 --00 --00 --00 --02 --07 --00 --20 --00 --1E --00 --00 --01 -T --15 --01 --00 --00 --00 --02 --1E --00 --00 --01 --07 --00 --20 --00 -B --16 --01 --00 --00 --00 --02 --07 --00 --20 --00 --3E --00 --00 --01 -T --16 --01 --00 --00 --00 --02 --3E --00 --00 --01 --07 --00 --20 --00 32 Mbit
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
B.7
Intel-Specific Extended Query Table
Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information.
Table 18. Primary-Vendor Specific Extended Query
Offset(1) P = 35H (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Length 3 Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Page mode read supported bit 8 Synchronous read supported Supported functions after suspend: read array, status, query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Addr. Hex Code Value "P" "R" "I" "1" "0"
1 1 4
35: --50 36: --52 37: --49 38: --31 39: --30 3A: --66 3B: --00 3C: --00 3D: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 0 bit 4 = 0 bit 5 = 1 bit 6 = 1 bit 7 = 0 bit 8 = 0 3E: --01
No Yes Yes No No Yes Yes No No
(P+9)h
1
(P+A)h (P+B)h
2
bit 0 = 1 3F: --03 40: --00 bit 0 = 1 bit 1 = 1 41: --33
Yes
Yes Yes 3.3 V
(P+C)h
1
(P+D)h
1
42:
--C0
12.0 V
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Table 19. Protection Register Information
Offset(1) P = 35H (P+E)h (P+F)h Length 1 Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with deviceunique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC -plane physical high address bits 16-23 = "n" such that 2n = factory pre- programmed bytes bits 24-31 = "n" such that 2n = user programmable bytes Addr. 43: 44: Hex Code --01 --80 Value 01 80h
(P+10)h 4 (P+11)h (P+12)h (P+13)h
45:
--00
00h
46: 47: 48:
--03 --03
8 byte 8 byte
Reserved for future use
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Appendix C Word-Wide Memory Map Diagrams
Table 20. 16-Mbit, and 32-Mbit Word-Wide Memory Flash Addressing
Top Boot Size (KW) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Bottom Boot 16 Mbit 32 Mbit
FF000-FFFFF 1FF000-1FFFFF FE000-FEFFF 1FE000-1FEFFF FD000-FDFFF 1FD000-1FDFFF FC000-FCFFF 1FC000-1FCFFF FB000-FBFFF 1FB000-1FBFFF FA000-FAFFF 1FA000-1FAFFF F9000-F9FFF 1F9000-1F9FFF F8000-F8FFF 1F8000-1F8FFF F0000-F7FFF 1F0000-1F7FFF E8000-EFFFF 1E8000-1EFFFF E0000-E7FFF 1E0000-1E7FFF D8000-DFFFF 1D8000-1DFFFF D0000-D7FFF 1D0000-1D7FFF C8000-CFFFF 1C8000-1CFFFF C0000-C7FFF 1C0000-1C7FFF B8000-BFFFF 1B8000-1BFFFF B0000-B7FFF 1B0000-1B7FFF A8000-AFFFF 1A8000-1AFFFF A0000-A7FFF 1A0000-1A7FFF 98000-9FFFF 198000-19FFFF 90000-97FFF 190000-197FFF 88000-8FFFF 188000-18FFFF 80000-87FFF 180000-187FFF 78000-7FFFF 178000-17FFFF 70000-77FFF 170000-177FFF 68000-6FFFF 168000-16FFFF 60000-67FFF 160000-167FFF 58000-5FFFF 158000-15FFFF 50000-57FFF 150000-157FFF 48000-4FFFF 148000-14FFFF 40000-47FFF 140000-147FFF 38000-3FFFF 138000-13FFFF 30000-37FFF 130000-137FFF 28000-2FFFF 128000-12FFFF 20000-27FFF 120000-127FFF 18000-1FFFF 118000-11FFFF 10000-17FFF 110000-117FFF 08000-0FFFF 108000-10FFFF 00000-07FFF 100000-107FFF This column continues on next page
1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF 0F8000-0FFFFF F0000-F7FFF 0F0000-0F7FFF E8000-EFFFF 0E8000-0EFFFF E0000-E7FFF 0E0000-0E7FFF D8000-DFFFF 0D8000-0DFFFF D0000-D7FFF 0D0000-0D7FFF C8000-CFFFF 0C8000-0CFFFF This column continues on next page
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Table 20. 16-Mbit, and 32-Mbit Word-Wide Memory Addressing (Continued)
Top Boot Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 Mbit 32 Mbit 0F8000-0FFFFF 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Size (KW) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 Bottom Boot 16 Mbit C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF 32 Mbit 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Appendix D Device ID Table
Read Configuration Address and Data Item Manufacturer Code Device Code 16 Mbit x 16-T 16 Mbit x 16-B 32 Mbit x 16-T 32 Mbit x 16-B x16 x16 x16 x16 00001 00001 00001 00001 88C2 88C3 88C4 88C5 x16 Address 00000 Data 0089
NOTE: Other locations within the configuration address space are reserved by Intel for future use.
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Appendix E Protection Register Addressing
Word-Wide Protection Register Addressing Word LOCK 0 1 2 3 4 5 6 7 Use Both Factory Factory Factory Factory User User User User A7 1 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 A1 0 0 1 1 0 0 1 1 0 A0 0 1 0 1 0 1 0 1 0
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e., A21-A8 = 0.
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
Appendix F Mechanical and Shipping Media Details
F.1 Mechanical Specification
Figure 21. 72-Ball Stacked-CSP: 12 x 8 Matrix
A1 INDEX MARK
S2 e A1
S1 A B C D E F G H b E
1
2
3
4
5
6
7
8
9 10 11 12
D
Top View: Ball Down
A2
Bottom View: Ball up
A
A1
Y
NOTE: 72- ball package consists of 8 x 12 solder ball matrix, 8 rows and 12 columns. Each row is identified by a letter and the column by a number. Each ball location, thus, is designated by row & column combination.
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Preliminary
28F1602C3, 28F1604C3, 28F3204C3
Millimeters Sym Package Height Standoff Package Body Thickness Ball Lead Diameter Package Body Length - 16 Mbit/2 Mbit Package Body Width - 16Mbit/2Mbit Package Body Length - 32 Mbit/4 Mbit, 16 Mbit/4 Mbit Package Body Width - 32 Mbit/4 Mbit, 16 Mbit/4 Mbit Pitch Seating Plane Coplanarity Corner to First Bump Distance - 16-Mbit/2-Mbit Corner to First Bump Distance - 16-Mbit/2-Mbit Corner to First Bump Distance - 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Corner to First Bump Distance - 32-Mbit/4-Mbit, 16-Mbit/4-Mbit A A1 A2 b D E D E e Y S1 S2 S1 S2 1.10 0.50 1.10 1.50 1.20 0.60 1.20 1.60 Min 1.20 0.30 0.92 0.325 9.90 7.90 11.90 7.90 Nom 1.30 0.35 0.97 0.40 10.00 8.00 12.00 8.00 0.80 0.1 1.30 0.70 1.30 1.70 0.0433 0.0197 0.0433 0.0591 Max 1. 40 0.40 1.02 0.475 10.10 8.10 12.10 8.10 Min 0.047 0.012 0.036 0.013 0.429 0.311 0.469 0.311
Inches Nom 0.051 0.014 0.038 0.016 0.433 0.315 0.472 0.315 0.031 0.004 0.0472 0.0236 0.0472 0.0630 0.0512 0.0276 0.0512 0.0669 Max 0.055 0.016 0.040 0.019 0.437 0.319 0.476 0.319
Preliminary
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28F1602C3, 28F1604C3, 28F3204C3
F.2
Media Information
Figure 22. Stacked CSP Device in Tray Orientation (8 mm x 10 mm and 8 mm x 12 mm
Device Pin 1
Tray Chamfer
NOTE: Drawing is not to scale and is only designed to show orientation of devices.
Figure 23. Stacked CSP Device in 24 mm Tape (8 mm x 10 mm and 8 mm x 12 mm)
Device Pin 1
58
Preliminary

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